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a
Dual 12-Bit (8-Bit Byte) Double-Buffered CMOS D/A Converter DAC8248
PIN CONNECTIONS 24-Pin 0.3" Cerdip (W Suffix), 24-Pin Epoxy DIP (P Suffix), 24-Pin SOL (S Suffix)
FEATURES Two Matched 12-Bit DACs on One Chip 12-Bit Resolution with an 8-Bit Data Bus Direct Interface with 8-Bit Microprocessors Double-Buffered Digital Inputs RESET to Zero Pin 12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature 5 V to 15 V Single Supply Operation Latch-Up Resistant Improved ESD Resistance Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin SOL Package Available in Die Form APPLICATIONS Multichannel Microprocessor-Controlled Systems Robotics/Process Control/Automation Automatic Test Equipment Programmable Attenuator, Power Supplies, Window Comparators Instrumentation Equipment Battery Operated Equipment GENERAL DESCRIPTION
The DAC8248's double-buffered digital inputs allow both DAC's analog output to be updated simultaneously. This is particularly useful in multiple DAC systems where a common LDAC signal updates all DACs at the same time. A single RESET pin resets both outputs to zero. The DAC8248's monolithic construction offers excellent DACto-DAC matching and tracking over the full operating temperature range. The DAC consists of two thin-film R-2R resistor ladder networks, two 12-bit, two 8-bit, and two 4-bit data registers, and control logic circuitry. Separate reference input and feedback resistors are provided for each DAC. The DAC8248
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The DAC8248 is a dual 12-bit, double-buffered, CMOS digitalto-analog converter. It has an 8-bit wide input data port that interfaces directly with 8-bit microprocessors. It loads a 12-bit word in two bytes using a single control; it can accept either a least significant byte or most significant byte first. For designs with a 12-bit or 16-bit wide data path, choose the DAC8222 or DAC8221.
FUNCTIONAL BLOCK DIAGRAM
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DAC8248-SPECIFICATIONS
ELECTRICAL CHARACTERlSTICS (@ V
Parameter STATIC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Symbol N INL DNL GFSE
= +5 V or +15 V; VREF A = VREF B = +10 V; VOUTA = VOUT B = 0 V; AGND = DGND = 0 V; TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)
DD
Conditions
Min 12
DAC8248 Typ Max
Units Bits LSB LSB LSB LSB LSB LSB ppm/C
DAC8248A/E/G DAC8248F/H All Grades are Guaranteed Monotonic DAC8248A/E DAC8248G DAC8248F/H (Notes 2, 3) All Digital Inputs = 0s TA = +25C TA = Full Temperature Range (Note 4) 2 5 8 11 0.2 VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V TA = +25C TA = Full Temperature Range DB0-DB11 WR, LDAC, DAC A/DAC B, LSB/MSB, RESET Digital Inputs = VINL or VINH Digital Inputs = 0 V or VDD VDD = 5%
2
1/2 1 1 1 2 4 5 10 50 15 1
Gain Temperature Coefficient (Gain/Temperature) Output Leakage Current IOUT A (Pin 2), IOUT B (Pin 24) Input Resistance (VREF A, REF B) Input Resistance Match DIGITAL INPUTS Digital Input High Digital Input Low Input Current (VIN = 0 V or VDD and VINL or VINH) Input Capacitance (Note 2) POWER SUPPLY Supply Current DC Power Supply Rejection Ratio (Gain/VDD)
TCGFS ILKG RREF
RREF RREF
nA k %
VINH VINL IIN CIN
2.4 13.5 0.8 1.5 0.001 1 10 10 15 2 100 0.002
V V V V A A pF pF mA A %/% ns s pF pF dB dB
IDD PSRR
10
AC PERFORMANCE CHARACTERISTICS Propagation Delay5, 6 tPD Output Current Setting Time6, 7 tS Output Capacitance CO
AC Feedthrough at IOUT A or IOUT B
FTA FTB
TA = +25C TA = +25C Digital Inputs = All 0s COUT A, COUT B Digital Inputs = All 1s COUT A, COUT B VREF A to IOUT A; VREF A = 20 V p-p f = 100 kHz; TA = +25C VREF B to IOUT B; VREF B = 20 V p-p f = 100 kHz; TA = +25C
350 1 90 120 -70 -70
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REV. B
DAC8248
Parameter Switching Characteristics (Notes 2, 8) LSB/MSB Select to Write Set-Up Time LSB/MSB Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time LDAC to Write Set-Up Time LDAC to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width LDAC Pulse Width Reset Pulse Width tCBS tCBH tAS tAH tLS tLH tDS tDH tWR tLWD tRWD Symbol Conditions VDD = +5 V +25 C -40 C to +85 C (Note 9) 130 0 180 0 120 0 160 0 130 100 80 170 0 210 0 150 0 210 0 150 110 90 DAC8248 VDD = +15 V -55 C to +125 C All Temps (Note 10) 180 0 220 0 160 0 220 0 170 130 90 80 0 80 0 80 0 70 10 90 60 60 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Units
NOTES 11 Measured using internal R FB A and RFB B. Both DAC digital inputs = 1111 1111 1111. 12 Guaranteed and not tested. 13 Gain TC is measured from +25C to TMIN or from +25C to TMAX. 14 Absolute Temperature Coefficient is approximately +50 ppm/C. 15 From 50% of digital input to 90% of final analog output current. V REF A = VREF B = +10 V; OUT A, OUT B load = 100 , CEXT = 13 pF. 16 WR, LDAC = 0 V; DB0-DB7 = 0 V to V DD or VDD to 0 V. 17 Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale. 18 See Timing Diagram. 19 These limits apply for the commercial and industrial grade products. 10 These limits also apply as typical values for V DD = +12 V with +5 V CMOS logic levels and T A = +25C. Specifications subject to change without notice.
Burn-In Circuit
REV. B
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DAC8248
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operates on a single supply from +5 V to +15 V, and it dissipates less than 0.5 mW at +5 V (using zero or VDD logic levels). The device is packaged in a space-saving 0.3", 24-pin DIP. The DAC8248 is manufactured with PMI's highly stable thinfilm resistors on an advanced oxide-isolated, silicon-gate, CMOS technology. PMI's improved latch-up resistant design eliminates the need for external protective Schottky diodes.
ABSOLUTE MAXIMUM RATINGS
(TA = +25C, unless otherwise noted.)
Package Type 24-Pin Hermetic DIP (W) 24-Pin Plastic DIP (P) 24-Pin SOL (S)
JA
1
JC
Units C/W C/W C/W
69 62 72
10 32 24
NOTE 1 JA specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and P-DIP packages; JA is specified for device soldered to printed circuit board for SOL package.
CAUTION
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V Digital Input Voltage to DGND . . . . . . . -0.3 V, VDD +0.3 V IOUT A, IOUT B to AGND . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . . 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . . 25 V Operating Temperature Range AW Version . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C EW, FW, FP Versions . . . . . . . . . . . . . . . . -40C to +85C GP, HP, HS Versions . . . . . . . . . . . . . . . . . . . 0C to +70C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C
1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFB. 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Do not insert this device into powered sockets; remove power before insertion or removal. 4. Use proper antistatic handling procedures. 5. Devices can suffer permanent damage and/or reliability degradation if stressed above the limits listed under Absolute Maximum Ratings for extended periods. This is a stress rating only and functional operation at or above this specification is not implied.
ORDERING GUIDE1
Model DAC8248AW2 DAC8248EW DAC8248GP DAC8248FW DAC8248HP DAC8248FP DAC8248HS3
Relative Accuracy (+5 V or +15 V) 1/2 LSB 1/2 LSB 1/2 LSB 1 LSB 1 LSB 1 LSB 1 LSB
Gain Error (+5 V or +15 V) 1 LSB 1 LSB 2 LSB 4 LSB 4 LSB 4 LSB 4 LSB
Temperature Range -55C to +125C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C
Package Description 24-Pin Cerdip 24-Pin Cerdip 24-Pin Plastic DIP 24-Pin Cerdip 24-Pin Plastic DIP 24-Pin Plastic DIP 24-Pin SOL
NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8248 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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REV. B
DAC8248
DICE CHARACTERISTICS
11. 12. 13. 14. 15. 16. 17. 18. 19. 10. 11. 12.
AGND IOUTA RFB A VREF A DGND DB7(MSB) DB6 DB5 DB4 DB3 DB2 NC
13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24.
NC DB1 DB0(LSB) RESET LSB/MSB DAC A/DAC B LDAC WR VDD VREF B RFB B IOUT B
SUBSTRATE (DIE BACKSIDE) IS INTERNALLY CONNECTED TO VDD.
Die Size 0.124 x 0.132 inch, 16,368 sq. mils (3.15 x 3.55 mm, 10.56 sq. mm)
WAFER TEST LIMITS @ V
Parameter Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Output Leakage (IOUT A, IOUT B) Input Resistance (VREF A, VREF B) VREF A, VREF B Input Resistance Match Digital Input High Digital Input Low Digital Input Current Supply Current DC Supply Rejection (Gain/VDD)
DD
= +5 V or +15 V, VREF A = VREF B = +10 V, VOUT A = VOUT B = 0 V; AGND = DGND = 0 V; TA = 25 C.
Conditions Endpoint Linearity Error All Grades are Guaranteed Monotonic Digital Inputs = 1111 1111 1111 Digital Inputs = 0000 0000 0000 Pads 2 and 24 Pads 4 and 22 DAC8248G Limit 1 1 4 50 8/15 1 2.4 13.5 0.8 1.5 1 2 0.1 0.002 Units LSB max LSB max LSB max nA max k min/k max % max V min V min V max V max A max mA max mA max %/% max
Symbol INL DNL GFSE ILKG RREF RREF RREF VINH VINL IIN IDD PSR
VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V VIN = 0 V or VDD; VINL or VINH All Digital Inputs VINL or VINH All Digital Inputs 0 V or VDD VDD = 5%
NOTES 1 Measured using internal R FB A and RFB B. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
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DAC8248-Typical Performance Characteristics
Channel-to-Channel Matching (DAC A & B are Superimposed)
Differential Nonlinearity vs. VREF
Differential Nonlinearity vs. VREF
Nonlinearity vs. VREF
Nonlinearity vs. VREF
Nonlinearity vs. VDD
Nonlinearity vs. Code (DAC A & B are Superimposed)
Nonlinearity vs. Code at TA = -55C, +25C, +125C for DAC A & B (All Superimposed)
Absolute Gain Error Change vs. VREF
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DAC8248
Full-Scale Gain Error vs. Temperature
Logic Input Threshold Voltage vs. Supply Voltage (VDD)
Supply Current vs. Temperature
Supply Current vs. Logic Input Voltage
Multiplying Mode Frequency Response vs. Digital Code
Output Leakage Current vs. Temperature
Analog Crosstalk vs. Frequency
REV. B
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DAC8248
Four Cycle Update Write Timing Cycle Diagram
PARAMETER DEFINITIONS RESOLUTION (N)
Five Cycle Update
GENERAL CIRCUIT DESCRIPTION CONVERTER SECTION
The resolution of a DAC is the number of states (2n) that the full-scale range (FSR) is divided (or resolved) into; where n is equal to the number of bits.
RELATIVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed in terms of least significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)
The DAC8248 incorporates two multiplying 12-bit current output CMOS digital-to-analog converters on one monolithic chip. It contains two highly stable thin-film R-2R resistor ladder networks, two 12-bit DAC registers, two 8-bit input registers, and two 4-bit input registers. It also contains the DAC control logic circuitry and 24 single-pole, double-throw NMOS transistor current switches. Figure 1 shows a simplified circuit for the R-2R ladder and transistor switches for a single DAC. R is typically 11 k. The transistor switches are binarily scaled in size to maintain a constant voltage drop across each switch. Figure 2 shows a single NMOS transistor switch.
Differential nonlinearity is the worst case deviation of any adjacent analog output from the ideal 1 LSB step size. The deviation of the actual "step size" from the ideal step size of 1 LSB is called the differential nonlinearity error or DNL. DACs with DNL greater than 1 LSB may be nonmonotonic. 1/2 LSB INL guarantees monotonicity and 1 LSB maximum DNL.
GAIN ERROR (GFSE)
Gain error is the difference between the actual and the ideal analog output range, expressed as a percent of full-scale or in terms of LSB value. It is the deviation in slope of the DAC transfer characteristic from ideal. Refer to PMI 1990/91 Data Book, Section 11, for additional digital-to-analog converter definitions.
Figure 1. Simplified Single DAC Circuit Configuration. (Switches Are Shown For All Digital Inputs at Zero)
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REV. B
DAC8248
DIGITAL SECTION
The DAC8248's digital inputs are TTL compatible at VDD = +5 V and CMOS compatible at VDD = +15 V. They were designed to convert TTL and CMOS input logic levels into voltage levels that will drive the internal circuitry. The DAC8248 can use +5 V CMOS logic levels with VDD = +12 V; however, supply current will increase to approximately 5 mA-6 mA.
Figure 2. N-Channel Current Steering Switch
The binary-weighted currents are switched between IOUT and AGND by the transistor switches. Selection between IOUT and AGND is determined by the digital input code. It is important to keep the voltage difference between IOUT and AGND terminals as close to zero as practical to preserve data sheet limits. It is easily accomplished by connecting the DAC's AGND to the noninverting input of an operational amplifier and IOUT to the inverting input. The amplifier's feedback resistor can be eliminated by connecting the op amp's output directly to the DAC's RFB terminal (by using the DAC's internal feedback resistor, RFB). The amplifier also provides the current-to-voltage conversion for the DAC's output current. The output voltage is dependent on the DAC's digital input code and VREF, and is given by: VOUT = VREF x D/4096 where D is the digital input code integer number that is between 0 and 4095. The DAC's input resistance, RREF, is always equal to a constant value, R. This means that VREF can be driven by a reference voltage or current, ac or dc (positive or negative). It is recommended that a low temperature-coefficient external RFB resistor be used if a current source is employed. The DAC's output capacitance (COUT) is code dependent and varies from 90 pF (all digital inputs low) to 120 pF (all digital inputs high). To ensure accuracy over the full operating temperature range, permanently turned "ON" MOS transistor switches were included in series with the feedback resistor (RFB) and the R-2R ladder's terminating resistor (see Figure 1). The gates of these NMOS transistors are internally connected to VDD and will be turned "OFF" (open) if VDD is not applied. If an op amp is using the DAC's RFB resistor to close its feedback loop, then VDD must be applied before or at the same time as the op amp's supply; this will prevent the op amp's output from becoming "open circuited" and swinging to either rail. In addition, some applications require the DAC's ladder resistance to fall within a certain range and are measured at incoming inspection; VDD must be applied before these measurements can be made.
Figure 3 shows the DAC's digital input structure for one bit. This circuitry drives the DAC registers. Digital controls, and , shown are generated from the DAC's input control logic circuitry.
Figure 3. Digital Input Structure For One Bit
The digital inputs are electrostatic-discharge (ESD) protected with two internal distributed diodes as shown in Figure 3; they are connected between VDD and DGND. Each input has a typical input current of less than 1 nA. The digital inputs are CMOS inverters and draw supply current when operating in their linear region. Using a +5 V supply, the linear region is between +1.2 V to +2.8 V with current peaking at +1.8 V. Using a +15 V supply, the linear region is from +1.2 V to +12 V (current peaking at +3.9 V). It is recommended that the digital inputs be operated as close to the power supply voltage and DGND as is practically possible; this will keep supply currents to a minimum. The DAC8248 may be operated with any supply voltage between the range of +5 V to +15 V and still perform to data sheet limits. The DAC8248's 8-bit wide data port loads a 12-bit word in two bytes: 8-bits then 4-bits (or 4-bits first then 8-bits, at users discretion) in a right justified data format. This data is loaded into the input registers with the LSB/MSB and WR control pins. Data transfer from the input registers to the DAC registers can be automatic. It can occur upon loading of the second data byte into the input register, or can occur at a later time through a strobed transfer using the LDAC control pin.
REV. B
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DAC8248
Figure 4. Four Cycle Update Timing Diagram
Figure 5. Five Cycle Update Timing Diagram
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DAC8248
AUTOMATIC DATA TRANSFER MODE
Data may be transferred automatically from the input register to the DAC register. The first cycle loads the first data byte into the input register; the second cycle loads the second data byte and simultaneously transfers the full 12-bit data word to the DAC register. It takes four cycles to load and transfer two complete digital words for both DAC's, see Figure 4 (Four Cycle Update Timing Diagram) and the Mode Selection Table.
STROBED DATA TRANSFER MODE
Strobed data transfer separating data loading and transfer operations serves two functions: the DAC output updating may be more precisely controlled, and multiple DACs in a multiple DAC system can be updated simultaneously.
RESET
The DAC8248 comes with a RESET pin that is useful in system calibration cycles and/or during system power-up. All registers are reset to zero when RESET is low, and latched at zero on the rising edge of the RESET signal when WRITE is high.
INTERFACE CONTROL LOGIC
Strobed data transfer allows the full 12-bit digital word to be loaded into the input registers and transferred to the DAC registers at a later time. This transfer mode requires five cycles: four to load two new data words into both DACs, and the fifth to transfer all data into the DAC registers. See Figure 5 (Five Cycle Update Timing Diagram) and the Mode Selection Table.
The DAC8248's control logic is shown in Figure 6. This circuitry interfaces with the system bus and controls the DAC functions.
Figure 6. Input Control Logic
MODE SELECTION TABLE
DIGITAL INPUTS
DAC A/B L L L L H H H H X X X X
WR L L L L L L L L H H X H
LSB/MSB L L H H L L H H X X X X
RESET H H H H H H H H H H L g
REGISTER STATUS DAC A DAC B Input Register DAC Input Register LDAC LSB MSB Register LSB MSB H L H L H L H L H L X X WR LAT LAT LAT LAT WR LAT WR LAT LAT LAT WR LAT LAT LAT LAT WR WR LAT LAT LAT LAT LAT WR LAT LAT LAT WR WR LAT LAT LAT LAT LAT WR LAT LAT WR LAT WR LAT LAT LAT LAT LAT LAT LAT WR LAT LAT ALL REGISTERS ARE RESET TO ZEROS ZEROS ARE LATCHED IN ALL REGISTERS
DAC Register LAT WR LAT WR LAT WR LAT WR LAT WR
L = Low, H = High, X = Don't Care, WR = Registers Being Loaded, LAT = Registers Latched.
REV. B
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DAC8248
INTERFACE CONTROL LOGIC PIN FUNCTIONS Table I. Unipolar Binary Code Table (Refer to Figure 7) Binary Number in
LSB/MSB - (PIN 17) LEAST SIGNIFICANT BIT (Active Low)/ MOST SIGNIFICANT BIT (Active High). Selects lower 8-bits (LSBs) or upper 4-bits (MSBs); either can be loaded first. It is used with the WR signal to load data into the input registers. Data is loaded in a right justified format. DAC A/DAC B - (PIN 18) DAC SELECTION. Active low for DAC A and Active High for DAC B. WR - (PIN 20) WRITE - Active Low. Used with the LSB/ MSB signal to load data into the input registers, or Active High to latch data into the input registers. LDAC - (PIN 19) LOAD DAC. Used to transfer data simultaneously from DAC A and DAC B input registers to both DAC output registers. The DAC register becomes transparent (activity on the digital inputs appear at the analog output) when both WR and LDAC are low. Data is latched into the output registers on the rising edge of LDAC. RESET - (PIN 16) - Active Low. Functions as a zero override; all registers are forced to zero when the RESET signal is low. All registers are latched to zeros when the write signal is high and RESET goes high.
DAC Register MSB LSB 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000
NOTE 1 LSB = (2-12) (VREF)=
Analog Output, VOUT
(DAC A or DAC B) -VREF 4096 -VREF = - VREF 4096 2 -VREF 4096 0V
1 (VREF) 4096
4095 2048 1 1
APPLICATIONS INFORMATION
UNIPOLAR OPERATION
Low temperature-coefficient (approximately 50 ppm/C) resistors or trimmers should be used. Maximum full-scale error without these resistors for the top grade device and VREF = 10 V is 0.024%, and 0.049% for the low grade. Capacitors C1 and C2 provide phase compensation to reduce overshoot and ringing when high-speed op amps are used. Full-scale adjustment is achieved by loading the appropriate DAC's digital inputs with 1111 1111 1111 and adjusting R1 (or R3 for DAC B) so that:
4095 VOUT = VREF x 4096
Figure 7 shows a simple unipolar (2-quadrant multiplication) circuit using the DAC8248 and OP270 dual op amp (use two OP42s for applications requiring higher speeds), and Table I shows the corresponding code table. Resistors R1, R2, and R3, R4 are used only if full-scale gain adjustments are required.
Full-scale can also be adjusted by varying VREF voltage and eliminating R1, R2, R3, and R4. Zero adjustment is performed by
Figure 7. Unipolar Configuration (2-Ouadrant Multiplication)
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DAC8248
loading the appropriate DAC's digital inputs with 0000 0000 0000 and adjusting the op amp's offset voltage to 0 V. It is recommended that the op amp offset voltage be adjusted to less than 10% of 1 LSB (244 V), and over the operating temperature range of interest. This will ensure the DAC's monotonicity and minimize gain and linearity errors.
BIPOLAR OPERATION Table II. Bipolar (Offset Binary) Code Table (Refer to Figure 8)
Binary Number in DAC Register MSB LSB 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0000
NOTE: 1 LSB=(2-11)(VREF) =
1 2048
Analog Output, VOUT (DAC A or DAC B) +VREF +VREF 0V -VREF -VREF
1 2048 2048 2048 2047 2048 1 2048
The bipolar (offset binary) 4-quadrant configuration using the DAC8248 is shown in Figure 8, and the corresponding code is shown in Table II. The circuit makes use of the OP470, a quad op amp (use four OP42s for applications requiring higher speeds). The full-scale output voltage may be adjusted by varying VREF or the value of R5 and R8, and thus eliminating resistors R1, R2, R3, and R4. If resistors R1 through R4 are omitted, then R5, R6, R7 (R8, R9, and R10 for DAC B) should be ratio-matched to 0.01% to keep gain error within data sheet specifications. The resistors should have identical temperature-coefficients if operating over the full temperature range. Zero and full-scale are adjusted in one of two ways and are at the users discretion. Zero-output is adjusted by loading the appropriate DAC's digital inputs with 1000 0000 0000 and varying R1 (R3 for DAC B) so that VOUT A (or VOUT B) equals 0 V. If R1, R2 (R3, R4 for DAC B) are omitted, then zero output can be adjusted by varying R6, R7 ratios (R9, R10 for DAC B). Full-scale is adjusted by loading the appropriate DAC's digital inputs with 1111 1111 1111 and varying R5 (R8 for DAC B).
(VREF)
SINGLE SUPPLY OPERATION CURRENT STEERING MODE
Because the DAC8248's R-2R resistor ladder terminating resistor is internally connected to AGND, it lends itself well for single supply operation in the current steering mode configuration. This means that AGND can be raised above system
Figure 8. Bipolar Configuration (4-Quadrant Multiplication)
REV. B
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DAC8248
ground as shown in Figure 9. The output voltage will be between +5 V and +10 V depending on the digital input code. The output expression is given by: VOUT = VOS x (D/4096)(VOS) where VOS = Offset Reference Voltage (+5 V in Figure 9) D = Decimal Equivalent of the Digital Input Word
VOLTAGE SWITCHING MODE
APPLICATIONS TIPS
GENERAL GROUND MANAGEMENT
Grounding techniques should be tailored to each individual system. Ground loops should be avoided, and ground current paths should be as short as possible and have a low impedance. The DAC8248's AGND and DGND pins should be tied together at the device socket to prevent digital transients from appearing at the analog output. This common point then becomes the single ground point connection. AGND and DGND is then brought out separately and tied to their respective power supply grounds. Ground loops can be created if both grounds are tied together at more than one location, i.e., tied together at the device and at the digital and analog power supplies. PC board ground plane can be used for the single point ground connection should the connections not be practical at the device socket. If neither of these connections are practical or allowed, then the device should be placed as close as possible to the systems single point ground connection. Back-to-back Schottky diodes should then be connected between AGND and DGND.
POWER SUPPLY DECOUPLING
Figure 10 shows the DAC8248 in another single supply configuration. The R-2R ladder is used in the voltage switching mode and functions as a voltage divider. The output voltage (at the VREF pin) exhibits a constant impedance R (typically 11 k) and must be buffered by an op amp. The RFB pins are not used and are left open. The reference input voltage must be maintained within +1.25 V of AGND, and VDD between +12 V and +15 V; this ensures that device accuracy is preserved. The output voltage expression is given by:
VOUT = VREF (D/4096)
where D = Decimal Equivalent of the Digital Input Word
Power supplies used with the DAC8248 should be well filtered and regulated. Local supply decoupling consisting of a 1 F to 10 F tantalum capacitor in parallel with a 0.1 F ceramic is highly recommended. The capacitors should be connected between the VDD and DGND pins and at the device socket.
Figure 9. Single Supply Operation (Current Switching Mode)
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DAC8248
Figure 10. Single Supply Operation (Voltage Switching Mode)
Figure 11. Digitally-Programmable Window Detector (Upper/Lower Limit Detector)
MICROPROCESSOR INTERFACE CIRCUITS
The DAC8248s versatile loading structure allows direct interface to an 8-bit microprocessor. Its simplicity reduces the number of required glue logic components. Figures 12 and 13 show the DAC8248 interface configurations with the MC6809 and MC68008 microprocessors.
REV. B
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Figure 12. DAC8248 to MC6809 Interface
Figure 13. DAC8248 to MC68008 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Cerdip (Q-24)
0.005 (0.13) MIN
24
0.098 (2.49) MAX
13
0.310 (7.87) 0.220 (5.59)
1 12
PIN 1 1.280 (32.51) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.070 (1.78) SEATING 0.030 (0.76) PLANE
0.320 (8.13) 0.290 (7.37)
15 0
0.015 (0.38) 0.008 (0.20)
24-Lead Plastic DIP (N-24)
1.275 (32.30) 1.125 (28.60)
24 1 13 12
24 Lead SOL (R-24)
0.6141 (15.60) 0.5985 (15.20)
PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE
1
12
0.015 (0.381) 0.008 (0.204)
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.280 (7.11) 0.240 (6.10)
24
13
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-16-
PRINTED IN U.S.A.
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